FPGA Implementation of a Phase Optimizer-Assisted PTS Scheme for PAPR Reduction in OFDM Systems

This article proposes a phase optimizer-assisted partial transmit sequence (PO-PTS) for minimizing PAPR values in OFDM systems. The novel PO-PTS scheme after validation, based on simulation results, is implemented using a Xilinx system generator on a field programmable gate array (FPGA). The phase optimizer (PO) module is employed to select optimal phase weighting factors to perform scaling with the data sequence in the PTS scheme. The computational complexity and the redundancy involved in producing the candidate signals are significantly reduced by the PO-PTS compared with the conventional PTS method. The proposed method reduces PAPR for a QPSK-OFDM signal by 56.16% compared to the original OFDM signal without compromising on the bit error rate (BER) performance. In addition, the performance of PO-PTS in terms of PAPR reduction for 32-QAM and 64-QAM modulated OFDM systems is also presented to justify the robustness of the proposed scheme. Moreover, when PO-PTS is implemented using FPGA, it uses only 1% of the hardware available in Virtex.