A 5-mm2, 4.7-W Convolutional Neural Network Layer Accelerator for Miniature Systems

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS(2023)

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摘要
This brief presents an energy-efficient accelerator for convolutional neural network (CNN) layer computations in a compact system. The accelerator replaces traditional data shift registers with a multiplexer-based barrel shifter, offering greater flexibility for supporting various models and reducing power consumption by 56.2% compared to flip-flop-based shifters. The prototype, fabricated using a 180-nm CMOS process, accelerates CIFAR-10 dataset CNN computations by 8.5 times compared to a system without the accelerator. It achieves this speedup while consuming only 4.7 mu W of power and 9.53 mu J for each inference task.
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关键词
Convolutional neural network, hardware accelerator, low power, miniature system
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