3-D Logic Circuit Design-Oriented Electrothermal Modeling of Vertical Junctionless Nanowire FETs

Sara Mannaa,Arnaud Poittevin,Cedric Marchand,Damien Deleruyelle,Bastien Deveautour,Alberto Bosio,Ian O'Connor,Chhandak Mukherjee,Yifan Wang,Houssem Rezgui,Marina Deng,Cristell Maneux,Jonas Mueller,Sylvain Pelloquin, Konstantinos Moustakas,Guilhem Larrieu

IEEE JOURNAL ON EXPLORATORY SOLID-STATE COMPUTATIONAL DEVICES AND CIRCUITS（2023）

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摘要

This work presents new insights into 3-D logic circuit design with vertical junctionless nanowire FETs (VNWFET) accounting for underlying electrothermal phenomena. Aided by the understanding of the nanoscale heat transport in VNWFETs through multiphysics simulations, the SPICE-compatible compact model captures temperature and trapping effects principally through a shift of the device threshold voltage. Circuit-level simulations indicate a strong impact of temperature variation on functionality and figures of merits, such as energy-delay products. Subsequent guidelines for design considerations are discussed that are intended to provide feedback for technology improvements.

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关键词

3-D electronics,compact model,electrothermal modeling,logic circuit design,vertical nanowire (NW) transistor

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