An AER-based spiking convolution neural network system for image classification with low latency and high energy efficiency

Spiking neural network is used to solve the problems of power consumption and computation requirement of the traditional artificial neural network. This paper proposes an event-driven multilayer spiking convolutional neural network (SCNN) hardware system for the image classification task. The proposed hardware system consists of a microcontroller unit (MCU) and an SCNN processor. Input images are temporally encoded to spike trains in the form of address event representation (AER) by MCU, and sent to the SCNN processor to execute AER-based spike-centric convolution in order to reduce redundant operations and get the classification result efficiently. By rearranging the storage structure of weights of synapses and membrane potential (MP) of spiking neurons, multi-channel parallel MP updating is realized to reduce latency. In addition, FIFOs are inserted between the spiking layers to construct a pipeline structure. The hardware architecture of the proposed system is implemented on the Xilinx ZYNQ-7000 platform. At the operating frequency of 100 MHz, the proposed SCNN processor has a speed of 400classifications/s and 80uJ/inference.