Single-Body-Integrated Complementary Tunneling Field-Effect Transistor (SBI CTFET) and Design Consideration of Processing Margin in Dual-Gate Formation

2023 IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia)(2023)

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摘要
In this work, a novel single-body-integrated complementary tunneling field-effect transistor (SBI CTFET) is proposed and optimally designed by series of rigorous device simulations. The proposed device demonstrates both n-type and p-type enhancement operations free from the ambipolar characteristics of a TFET sharing the channel in common, enabling highly reliable operations and plausibly scaled cell area. The subthreshold swing (S) values for n-type and p-type in the single cell were 55 mV/dec. Moreover, the processing margin in forming its dual gates is systematically suggested for future designers.
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关键词
single-body-integration,complementary tunneling field-effect transistor,enhancement mode,reliable operation,area scaling,processing margin
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