Agile Full-Chip Sign-Off in the Post-Moore Era

Sign-off is a crucial step in the chip design flow to guarantee the performance and reliability of chips prior to tape-out. However, the ever-growing integration density and voltage scaling in the post-Moore era have made conventional sign-off inaccurate and expensive, presenting challenges such as dynamic parasitics effects, large-scale circuits, and multi-objective coupling. To overcome these challenges, this paper introduces the concept of agile dynamic sign-off, which has significant potential for chip design and validation, combining dynamic modeling, artificial intelligence assisted acceleration, and multi-objective coupling analysis. Two representative works are provided to demonstrate the application of agile dynamic sign-off in system modeling and simulation.