Design and Optimization of RC Triggered MV-NMOS for 28NM CMOS Technology ESD Protection

An effective design of RC triggered medium voltage ESD nMOS power clamp in 28nm high voltage CMOS technology is presented in this work. Through transmission line plus test, it is found that there are two modes in the conduction of the power clamp NMOS: MOS channel conduction and parasitic NPN turn on conduction. Different conduction modes given the device very different robustness. Herein, by optimizing the layout and process condition, the ESD power clamp performance (It2) significantly improved from 0.2A to 1.17A with same area. This is because the parasitic NPN can be turned on in time to release most of the current.