Design of low power approximate multiplier based on compressors for multimedia application

In recent years, there has been a growing demand for digital signal processors that are capable of processing multimedia data with great efficiency and minimum power usage. Multiplication, one of the most important DSP processes, is crucial for applications like audio and picture processing. However, performing exact multiplication requires a significant amount of power and hardware resources. Therefore, there has been increasing interest in designing low-power approximate multipliers that provides accurate outcomes with reduced power consumption and hardware resources. In this work, we describe a low-power approximation multiplier architecture based on approximate compressors. We are modifying the exact compressor by following steps: i.) Reducing the equations of sum and carry by applying different Boolean expressions. ii.) Adding errors in the truth table of exact one and then deriving the equation. iii.) Designing multiplier using mixing of true and false compressor. Power-efficient circuits for approximative multiplication is created using an approximate 4:2 compressor. After adding of the error recovery module also, the architecture is precise with reduced hardware requirements. Also it draws less power as compared with earlier suggested 4:2 compressor based approximative multiplier systems.