A Sub-600mV, Fluctuation tolerant 65nm CMOS SRAM Array with Dynamic Cell Biasing

Azeez Bhavnagarwala,Stephen Kosonocky,Yuen Chan,Kevin Stawiasz,Uma Srinivasan,Steve Kowalczyk,Matt Ziegler

2007 IEEE Symposium on VLSI Circuits（2007）

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摘要

Combinations of circuit techniques enabling tolerance to V _tau fluctuations in SRAM cell transistors during read or write operations and significant reductions in minimum operating voltage are reported. Implemented in a 9 Kb times 74 b PDSOI CMOS SRAM array with a conventional 65 nm SRAM cell and an ABIST, these techniques, demonstrate VMIN of 0.58 V and 0.40 V/0.54 V for single and dual V _DD implementations respectively. The techniques consume a 10-12% overhead in area, improve performance marginally and also enable over 50% reduction in cell leakage with minimal circuit overhead.

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关键词

CMOS SRAM cell array,dynamic cell biasing,Vtau fluctuations tolerance,SRAM cell transistors,minimum operating voltage,PDSOI CMOS SRAM array,cell leakage reduction,minimal circuit overhead,single VDD implementations,dual VDD implementations,read-write operations,circuit techniques,conventional ABIST,size 65 nm,voltage 600 mV

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