Examining the Feasibility of Modeling the Inner Current Control Loop of a Grid-Following Inverter in the Phasor-Based Solver

Historically, when modeling a grid-following (GFL) inverter in the phasor-based solver, the fast inner current control loop is typically ignored. To achieve a more accurate modeling, the authors have attempted to model the inner current control loop in the phasor-based solver, but experienced significant numerical stability issues. This paper conducts a detailed analysis and provides insight into the feasibility of modeling the inner current control loop of a GFL inverter in the phasor-based solver. The key findings of this study reveal that: a) neglecting the inverter filter dynamic can cause the the bandwidth of the inner current control loop to become infinite with typical parameters in the phasor domain, resulting in an inaccurate representation of the actual inner current control loop, whose bandwidth typically ranges between 600 Hz to 2 kHz and b) the relatively large simulation time step in the phasor simulation causes numerical stability issues when simulating an inner current loop with such an infinite bandwidth. Detailed electromagnetic (EMT) and phasor modeling, and frequency response analyses are performed to explain this phenomenon. The findings of this paper explain why it is inappropriate to model the fast inner current control loop of a GFL inverter in the phasor-based solver.