Exploration of FPGA PLB Architecture Base on LUT and Microgates

Because of the logic redundancy of look-up table (LUT) based field programmable gate array (FPGA), we explore a series of programmable logic block (PLB) architectures to increase logic density by adding different kinds of microgates including AND gate and exclusive-OR gate. Because individual LUT inputs have different delays to the output, adding microgates to the shortest input-output path does not influence the LUT critical path delay. To evaluate the proposed PLB architectures, the Boolean matching based on disjoint-support decomposition (DSD) library in ABC is used to realize technology mapping and followed by VPR 8.0 to pack, place and route. Evaluation results based on VTR and Koios benchmarks show that the proposed PLB architecture by adding two AND gates to LUT6 can achieve the best performance, which reduces the logic depth, the utilization of PLBs, and the critical path delay by 19.8%, 4.36%, and 6.25% respectively on average compared to Intel Stratix-10 PLB architecture in VTR.