New Compatible Stress-Complementary BCD Technology for Deep Trench Isolation

A new compatible stress-compensated bipolar-CMOS-DMOS (C-SC BCD) technique is proposed and experimentally proved in this letter. Based on the conventional BCD technology, C-SC introduces three steps of back etching, back sealing and front sealing, and is fully compatible with the BCD process. C-SC can gradually relieve and compensate the stress introduced by the deep trench isolation structure of thick film silicon-on-insulator (SOI) devices. The mechanism of C-SC technology lies in the reasonable distribution of thermal stress, tensile stress and compressive stress, which makes the stress acting on the wafer compensate each other and greatly reduces the original significant wafer bow. Verified by experiments on SOI and silicon materials with different thicknesses, surface bow caused by deep trench isolation structure is almost eliminated after using C-SC technology. The C-SC technology is demonstrated by experiments of a SOI with 1S $\mu \mathrm{m}$ silicon and 3.5 $\mu \mathrm{m}$ the buried oxide layer (BOX) layer, which revealed that the C-SC BCD technology can reduce the probability of online anomalies and improve the uniformity of devices and integrated circuits on the wafer.