A 32GHz Two-stage Frequency Synthesizer with 100MHz Reference using Injection Locked Technology

The article presents the design of a high-speed clock signal generation circuit which is capable of delivering high-speed clock signals at 8GHz and 32GHz. A two-stage architecture is used in the design to suppress in-band phase noise and improve the integral power efficiency respectively. In the first stage, a sub-sampling phase locked loop(SSPLL) with a dead-zone controlled frequency tracking loop is adopted to realize better frequency establishment and in-band phase noise performance. The second stage utilizes the intermediate signal and injection-locked voltage-controlled-oscillator(ILVCO) to achieve frequency multiplication in millimeter-wave frequency band. To guarantee the frequency selection characteristics of the LC tank and ease the ratio between the frequency of injected signals and the conduction time of differential injected transistors, two injection-locked frequency doublers with push-push topology are cascaded and four times frequency multiplication is presented. The frequency synthesizer is designed by TSMC 28nm CMOS process and achieves 70-fs jitter in the time domain with 42.6-mW power consumption at 32GHz and a figure of merit of -246.8dB.