Assessment of the Zero Distortion Bias Point Using Design-Oriented 7-Parameter MOSFET Model

This paper uses a design-oriented 7-parameter MOSFET model to assess the Zero Distortion Bias Point (ZDBP). The ZDBP existence and its dependencies on the main Short-Channel Effects (SCE) typically found in advanced CMOS technologies such as Drain-Induced Barrier Lowering (DIBL), carrier velocity saturation, carrier mobility reduction, and Channel Length Modulation (CLM) are herein investigated. The design-oriented model used here is based on the inversion charge concept which preserves the physics of the MOS transistor, while keeping valid for all bias regimes (from weak to strong inversion) and all operating regions (linear and saturated). Across technologies, this paper’s results demonstrate that ZDBP appears around the Threshold Voltage (V TH ) when carrier mobility reduction and carrier velocity saturation are included in the model and its localization orbits around the V TH − 55mV < V TH < V TH + 100mV depending mainly on the DIBL and carrier mobility reduction parameters.