A 0.99μs FFT-Based Fast-Locking, 0.82GHz-to-4.1GHz DPLL-Based Input-Jitter-Filtering Clock Driver with Wide-Range Mode-Switching 8-Shaped LC Oscillator for DRAM Interfaces

Owing to the jitter-filtering nature, a phase-locked loop (PLL) often plays as a clock driver in memory systems, cleaning out highfrequency noise present in the overall clock distribution path. For LC oscillators, a parallel multi-core topology enhances the output phase noise but still suffers from a narrow frequency tuning range (FTR). To overcome this, [1] employs a mode switching, but the negligible equivalent inductance in the odd mode requires excessively large capacitance for low-frequency oscillation. While the coupling method in [2] also gives a wide FTR, the achievable area efficiency is limited due to the spiral inductor structure. in a digital PLL (DPLL), a widerange time-to-digital converter (TDC) achieves fast frequency acquisition but at the expense of a larger area and power. Although gear-shifting [3]–[4] or digital frequency-error recovery [5] may reduce the lock time without much hardware overhead, an effective method for a wide FTR still remains to be sought.