Threshold Voltage Drift and On-Resistance of SiC Symmetrical and Asymmetrical Double-trench MOSFETs Under Gate Bias Stress

In this paper, long-period positive and negative DC gate bias stressing is applied on the SiC symmetrical and asymmetrical double-trench MOSFETs for a wide range of temperatures in comparison with SiC planar MOSFETs. The magnitude of gate stress are within the recommended ranges by manufacturers with clear threshold voltage drift being observed. Also, the post-stress drift of on-state resistance at both high and low applied gate-source voltages is measured. The impact of temperature on these parameters are shown to vary for different structured MOSFETs.