Low-Latency LeNet-5 Architecture for Handwritten Digit Recognition

This paper presents an implementation of low-latency LeNet-5 architecture for real-time handwritten digit recognition. The proposed architecture comprises three convolutional layers, two max pooling layers, and a fully connected layer. Because we adopted pipeline processing between adjacent layers, the proposed architecture required roughly n ² + 2n clock cycles for processing an image of n × n. For the implementation of handwritten digit recognition using 90nm complementary metal-oxide-semiconductor (CMOS) technology, the proposed LeNet-5 design of 28 × 28 input data with a 5 × 5 kernel required a gate count of roughly 7.9M, resulting in power consumption of 5.5 W at 200 MHz. ¹