FeFET based Logic-in-Memory design methodologies, tools and open challenges

Cedric Marchand, Alban Nicolas, Paul-Antoine Matrangolo,David Navarro,Alberto Bosio,Ian O'Connor

2023 IFIP/IEEE 31ST INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION, VLSI-SOC(2023)

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摘要
Data-centric applications such as Artificial Intelligence and IoT are putting stringent performance and energy efficiency constraints on hardware implementations of computing architectures. Computing in Memory paradigm appears as a viable approach to to address such constraints and ferroelectric FETs (FeFETs) push this paradigm at a finer grain by enabling the design of true non-volatile logic gates, by implementing tight combination of memory and logic called Logic-in-Memory (LiM). From the basic non-volatile logic gate design up to the application-level evaluation, several challenges have to be addressed. In this paper, we present a methodology to design complex operations such as cryptographic operations using FeFET, integrate them into a complete computing architecture and evaluate its benefits. Current challenges related to logic synthesis and tools for synthesis of these LiM structures will also be discussed.
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