Bit Error Rate Performance of Real-Valued Spreading Sequences in DSSS-CSK Based Wireless Communications

This paper proposes real-valued spreading sequences for direct-sequence spread spectrum (DSSS) and code shift keying (CSK) applications. In our simulation, the real-valued spreading sequences improve the EbN0 performance by 0.75 dB compared to the CSK system designed for Barker codes and m-sequences. Using real-valued sequences requires the implementation of signed fixed-point arithmetic with a precision of at least 6 bits, leading to significantly higher hardware overhead for modulators and demodulators than in the case of binary DSSS and CSK systems. On the one hand, our solution requires up to five times more hardware resources and energy. On the other hand side, the additional ga[1] in on the physical layer can be used to simplify the forward error correction engine.Nowadays, digital processors and field programmable gate arrays (FPGAs) can handle the 6-bit precision relatively easily, and in our case, we were able to implement the proposed modulator and demodulator in less than 1% of hardware resources available in Virtex Ultrascale+ FPGA.