A study of gate recess-width control of InP-based HEMTs by a Si

Recess process for opening a narrow trench in the capping layer for T-shaped gates is one of the most important steps in the fabrication of InP-InAlAs/InGaAs based high electron mobility transistors, since the recessed-width strongly influences the DC/RF performances of the devices. Conventional chemical wet etch fails to well control the recess-width and its uniformity, leaving the seemingly small issue still rarely addressed so far. This work quantitatively analyzed the relationship between the recess-width and the DC/RF properties of the device by numerical simulations. To enhance the controllability of the recess-width, a 20-nm thick Si 3 N 4 passivation layer pre-grown on the top of the capping layer was proposed. Careful comparisons of the recess-width as well as the device property with and without the passivation layer was carried out. Our results from both experiments and simulations indicate that it is promisingly feasible to control the recess-width to the desired scale by chemical wet etch when a dielectric layer such as Si 3 N 4 is applied to protect the InGaAs capping layer from being over recessed, leading to enhanced device performance. With such an additional Si 3 N 4 passivation layer, it is expected that the manufacturing yield of the InP-based high electron mobility transistors should be significantly enhanced with improved device performances. Display Omitted • Results indicate that the dielectric layer can enhance the controllability of the recess-width by eliminating the erosion. • This work analyzed the relationship between the recess-width and the properties of the device by numerical simulations. • This work is important to realize the device structure for high performance of the HEMTs and high yield in manufacturing.