Work-in-Progress: A Generic Non-Intrusive Parallelization Approach for SystemC TlM-2.0-Based Virtual Platforms

The ever-growing complexity of Systems-on-a-Chip (SoCs) requires continuous improvements of development tools such as Virtual Platforms (VPs). VPs are Software (SW)-based functional simulators of SoCs that allow SW development in an early design stage. Any improvement of VP's performance reduces the needed simulation time and thereby accelerates the development process. In this work, we present a novel approach that can be used to parallelize the CPU model of a SystemC-TLM-2.0-based VP. We present our first results showing that the technique can achieve speedups of up to 7. 5x for an octa-core ARM VP.