FlooNoC: A Multi-Tb/s Wide NoC for Heterogeneous AXI4 Traffic

IEEE Design & Test(2023)

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摘要
Editor’s notes: This article introduces an open-source, low-latency Network-on-Chip (NoC) designed to tackle bandwidth challenges faced by traditional narrow and serialized NoCs. The authors demonstrate the effectiveness of wide channels by integrating a 5 × 5 router and links within a 9-core compute cluster using 12-nm FinFet technology. —Mahdi Nikdast, Colorado State University, USA —Miquel Moreto, Barcelona Supercomputing Center, Spain —Masoumeh (Azin) Ebrahimi, KTH Royal Institute of Technology, Sweden —Sujay Deb, IIIT Delhi, India
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关键词
Network-On-Chip,AXI,Network Interface,Physical design
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