ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation
arxiv(2023)
摘要
We introduce ABACuS, a new low-cost hardware-counter-based RowHammer
mitigation technique that performance-, energy-, and area-efficiently scales
with worsening RowHammer vulnerability. We observe that both benign workloads
and RowHammer attacks tend to access DRAM rows with the same row address in
multiple DRAM banks at around the same time. Based on this observation,
ABACuS's key idea is to use a single shared row activation counter to track
activations to the rows with the same row address in all DRAM banks. Unlike
state-of-the-art RowHammer mitigation mechanisms that implement a separate row
activation counter for each DRAM bank, ABACuS implements fewer counters (e.g.,
only one) to track an equal number of aggressor rows.
Our evaluations show that ABACuS securely prevents RowHammer bitflips at low
performance/energy overhead and low area cost. We compare ABACuS to four
state-of-the-art mitigation mechanisms. At a near-future RowHammer threshold of
1000, ABACuS incurs only 0.58
energy overheads, averaged across 62 single-core (8-core) workloads, requiring
only 9.47 KiB of storage per DRAM rank. At the RowHammer threshold of 1000, the
best prior low-area-cost mitigation mechanism incurs 1.80
performance overhead than ABACuS, while ABACuS requires 2.50X smaller chip area
to implement. At a future RowHammer threshold of 125, ABACuS performs very
similarly to (within 0.38
and energy-efficient RowHammer mitigation mechanism while requiring 22.72X
smaller chip area. ABACuS is freely and openly available at
https://github.com/CMU-SAFARI/ABACuS.
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