A Distributed Cascode Power Amplifier with an Integrated Analog SIC Filter for Full-Duplex Wireless Operation in 65 nm CMOS

In this work, we propose a fully integrated transmitter front-end based on a balanced distributed cascode power amplifier and a passive second-order reconfigurable reflective self-interference cancellation (SIC) filter for full-duplex wireless applications. The balanced topology provides inherent passive transmit-receive (TX-RX) isolation complemented by the passive SIC filter, which accounts for the signal, noise, and nonlinearity components of the direct TX-RX leakages and the reflections from a commercial Wi-Fi antenna. A front-end chip prototype fabricated in TSMC's 65 nm CMOS process operating between 5-6 GHz and occupying the area of 1.2 mm(2) achieves 19.5 dBm P-sat with 31% peak PAE, 17 dBm OP1dB, and 8-10 dB RX noise figure, along with 40 dB of TX-RX isolation and -30 dB TX EVM at 10 dB power backoff using a 20 MHz Wi-Fi OFDM signal without DPD.