Two-Port Characterization of Symmetric Varactors in 65-nm CMOS Process for Mixer Applications

2023 IEEE TEXAS SYMPOSIUM ON WIRELESS AND MICROWAVE CIRCUITS AND SYSTEMS, WMCS(2023)

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Abstract
Accumulation-mode MOS symmetric varactors (SVAR) with two ports are designed and fabricated in a 65-nm CMOS process. The SVAR is composed of an n-type varactor (n-VAR) and a p-type varactor (p-VAR) with their gates combined to port 1. Port 2 is connected to the n-well of the n-VAR. The 2-port SVAR provides an additional path for IF signal injection, which can simplify and potentially improve the isolation structure between RF to IF. A 1-port p-VAR test structure is also designed to verify its operation. The dynamic cut-off frequency of the SVAR is extracted to be 505 GHz with 2-port measurements up to 40 GHz. The SVAR exhibits a quality factor greater than 21 at 40 GHz and a maximum-to-minimum capacitance ratio of 1.4. The n-well port of the SVAR has a quality factor of 30 at 10 GHz. 1-port measurements of the p-VAR show that the capacitance of the p-type varactor is about 19% smaller than that of the n-VAR.
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