A 4.8 GS/s 11b Time-Interleaved TDC-Assisted SAR ADC with High-Speed Latch-based VTC

This paper proposes an 8-channel time-interleaved (TI) TDC-assisted SAR ADC. Each channel consists of a 7-bit loop-unrolled SAR ADC and a 5-bit flash time-to-digital converter (TDC). To improve the voltage-to-time conversion speed and enhance the time-domain quantization accuracy, a latch-based voltage-to-time converter (VTC) and a linear time-domain amplifier (TA) are developed without affecting the power efficiency benefit of the time-domain quantization. In the second stage of the ADC, a 5-bit flash TDC with non-uniform delay cells is developed to optimize the overall speed and compensate for the VTC non-linearity. In addition, a fast noise-reduction technique is designed in the SAR ADC stage to increase the power efficiency without degrading the speed. Fabricated in a 22nm FDSOI CMOS technology, the ADC achieves an SNDR and SFDR of 52.65 dB and 62.72 dB at 4.8 GS/s, respectively, leading to a $\mathrm{F}\mathrm{O}\mathrm{M}_{W}$ of 43.59 fJ/conv.step