An Efficient Accelerator for Nonlinear Model Predictive Control

The computational complexity of Nonlinear Model Predictive Control (NMPC) often hinders their application to cyber-physical systems with fast dynamics, such as mobile robots or Unmanned Aerial Vehicles. This complexity overhead comes from the control algorithm's backbone, an iterative solver that must ensure convergence and often takes the form of a highly structured convex Quadratic Program (QP). Such overhead could be overcome using specialized computer architectures. Field Programmable Gate Arrays are good candidates for making hardware accelerators that comply with the realtime constraints of fast-dynamic cyber-physical systems. Nevertheless, QP-solvers have been demonstrated to be complex to implement as a hardware accelerator. With this in mind, the present paper proposes a novel accelerator architecture that uses Knowledge-based Particle Swarm Optimization (PSO) as a solver while exploring its parallel nature. PSO is a stochastic global optimization algorithm that creates a fast and precise solution for NMPC. The proposed strategy in this papergrants system control stability for short sampling frequencies and long prediction horizons. It can also meet realtime constraints while achieving low hardware consumption. Additionally, it is generalized, so it can potentially be adapted to any application and is compatible with the Robot Operating System (ROS). The architecture is tested with two applications: an inverted pendulum swing-up procedure and a quadrotor drone with control and state constraints. Following, we analyze the accelerator performance and highlight our solution's advantages to other works in the literature. Namely, our architecture solves more complex problems with a greater dimension and longer horizon while using similar resources. The proposed solution also has good computational performance (29ms and 11ms) for both the quadrotor and inverted pendulum, respectively, while achieving the realtime requirements (50ms and 100ms, respectively). Parallelly, ad-hoc embedded architectures are important for a low-end, low-cost, and low-power MPSoC+FPGA device. Our solution uses less than 50% of a low-end, low-power MPSoC device (ZU3EG), while others rely on large, more power-hungry devices (e.g., Kintex7 and XC7Z045).