An Energy-Efficient Interpolation Unit Targeting VVC Encoders with Approximate Adder

The advances in current video encoders allow significant compression at the cost of increased computing and energy consumption. This creates a demand for the development of dedicated accelerators that efficiently explore the parallelism of computing-intensive encoding operations. This work presents a hardware accelerator for the interpolation step of Versatile Video Coding (VVC) systems using Lower-Part-OR Adders (LOA). Unlike competing solutions, the proposed design fully complies with current VVC interpolation types, including the alternative filter of this standard. A data gating mechanism is also implemented to prevent unnecessary circuit switching. Experimental results show that savings of up to 78.51 % in power and 67.08% in gate count can be achieved by using approximate computing techniques.