DCVS Level Shifter for Clock Path

In a multiple voltage-island system with dynamic voltage scaling, difference between rise and fall delays of a level shifter in a clock path can have large variation since the supply voltage for each island changes dynamically, leading to performance degradation. This paper analyzes the variation of rise and fall delays of the level shifter due to the voltage change, and presents a novel differential cascade voltage switch (DCVS) level shifter with balanced rise and fall delays for arbitrary voltage conversion. The proposed DCVS level shifter has been designed using a 90nm CMOS process technology. The silicon measurement results indicate the maximum difference decreases up to 86%.