On Continuing DNN Accelerator Architecture Scaling Using Tightly Coupled Compute-on-Memory 3-D ICs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems(2023)
摘要
This work identifies the architectural and design scaling limits of 2-D flexible interconnect deep neural network (DNN) accelerators and addresses them with 3-D ICs. We demonstrate how scaling up a baseline 2-D accelerator in the
$X/Y$
dimension fails and how vertical stacking effectively overcomes the failure. We designed multitier accelerators that are
$1.67\times $
faster than the 2-D design. Using our 3-D architecture and circuit codesign methodology, we improve throughput, energy efficiency, and area efficiency by up to
$5\times $
,
$1.2\times $
, and
$3.9\times $
, respectively, over 2-D counterparts. The IR-drop in our 3-D designs is within 10.7% of VDD, and the temperature variation is within 12 °C.
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关键词
dnn accelerator architecture scaling,compute-on-memory
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