RF2P: A Lightweight RISC Processor Optimized for Rapid Migration from IEEE-754 to Posit

2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)(2023)

引用 0|浏览7
暂无评分
摘要
This paper presents a lightweight processor and evaluation platform for migrating from IEEE-754 to posit arithmetic, with an optimized posit arithmetic unit (PAU) supporting existing floating-point instructions. The PAU features a reconfigurable divider architecture for diverse operating conditions and lightweight square root logic. The platform includes a posit-optimized compiler, divider generator, JTAG environment builder, and programmable logic controller. The experimental results demonstrate the successful execution of legacy IEEE-754 code with a small additional workload and up to 60.09 times the performance improvement through hardware acceleration. Additionally, the PAU and divider consume 11.00% and 57.87% fewer LUTs, respectively, compared to the best prior works.
更多
查看译文
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络