An Improved Single and Double-Adjacent Error Correcting Codec with Lower Decoding Overheads

Importance of Error Correcting Codes (ECCs) is increasing rapidly for protecting memories from localized errors. These localized errors in memories are mainly due to radiation induced soft errors which corrupt data stored in a single cell or multiple cells of a memory. Initially, Single Error Correction (SEC) and Single Error Correction-Double Error Detection (SEC-DED) codes have been widely introduced to protect memories against soft errors. But with the incessant down scaling of technology node, the chances of multiple errors in memory cells are increasing day by day. The most common errors in multiple memory cells are the single error and double-adjacent errors. These errors are corrected by employing Single Error Correction- Double Adjacent Error Correction (SEC-DAEC) codes. But the major challenges in designing SEC-DAEC codes are higher decoding overheads and higher miscorrection rate. In this paper, the H -matrices for a new class of SEC-DAEC codes have been proposed to reduce the decoding overheads. The proposed codecs have been designed and synthesized in ASIC platform with suitable word lengths for memories. Both the theoretical and synthesis results for proposed codecs have been compared with recently published related works. These comparisons show that proposed (24, 16) codec requires a maximum of 1.38 times and 1.74 times lower area and delay respectively compared to other related codecs of same word length. Also the proposed 64-bit codec consumes a highest of 2.75 times lesser power with respect to existing 64-bit codecs. Thus the proposed codecs can be employed in memories for correcting single and double-adjacent errors with improved area, delay and power requirements.