Characterization and Exploration of Latch Checkers for Efficient RAS Protection.

Reliability has been, and continues to be a key consideration in the design of the IBM Z mainframe processors, and this has resulted in industry-leading performance with little-to-no downtime. In this paper, we analyze the various hardware reliability mechanisms that make the processor resilient to transient errors, and the checker architecture that enables their detection and correction. We characterize the error checking logic in the processor based on a detailed analysis of the actual design. Based on hardware measurements on a real Z processor, we then determine the error checkers that are critical from a timing standpoint. We propose algorithms that optimize checker selection without affecting either the RAS coverage or the detection of timing errors. Finally, we examine further potential runtime optimizations of checkers based on the logic utilization in representative benchmarks.