Synthesizable ADPLL Generator: From Specification to GDS

We propose an all-digital phase-locked loop (ADPLL) generator that automatically selects a design solution from a given input specifications and generates the layout using place-and-route (PnR) tool within 1.2 hours. While SPICE simulation-based modeling for a PLL is impractical due to its heavy computational intensity, all-digital architecture enables the use of theory-based frequency domain model for predicting the output specification, once the oscillator performance is characterized. The cell-based digitally controlled oscillator (DCO) is modeled by extracting the PDK and cell specific constants that characterizes the effective current to capacitance ratio from 3 sets of SPICE simulations. The constants are then used to predict the analog performance with an analytical model, which shows error rate less than 1.5% for estimating frequency range and power consumption. 8 generated PLL designs and their post-parasitic performances are compared to input specifications, including one measurement result from a fabricated chip in 65nm CMOS process.