Design considerations for a CMOS 65-nm RTN-based PUF

Physical Unclonable Functions (PUFs) have emerged as more secure alternatives to traditional Non-Volatile Memories in the field of hardware security. Recently, a novel PUF has been presented that uses the Random Telegraph Noise (RTN) phenomenon as the underlying source of entropy. To turn this concept into an integrated circuit, this paper provides a description of the transistor-level implementation of the PUF as well as a discussion on the constraints and requirements (both in functionality and testing capability) that a silicon implementation brings about. More specifically, the paper explores how to design and physically arrange the core elements of the RTN-PUF to efficiently use the silicon area and attain low PUF response times after a challenge is given.