Variable Duty Cycle Pulse Generation for Low Complexity Randomization in Machine Learning.


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Randomization constitutes a major part in stochastic machine learning (ML) training processes. Typically, linear feedback shift register (LFSR) is used for periodic pseudorandom bits generation. However, they are known to have high switching activity as well as complexity as the precision requirements increase. This work proposes an alternative method for randomization using variable duty cycle-based pulse generation. Key principles include generation of oscillating signal and obtaining a delayed version of the same leading to different duty cycles. Two designs for creating a variable duty cycle are proposed. The first technique utilizes a buffer-based delay element as a duty cycle regulator, whereas the second relies on a basic RC circuit. The shifted version of the same signal is generated and passed through logic gates providing varied pulse widths. The obtained signal's pulse width is designed to allow the duty cycle to range between 20% and 90%. When compared to RC-based variation +/-(8.5)%, buffer-based performs better against PVT variation with a significant small deviation +/-(0.8)%. A multiplexer is used to pick the required duty cycle depending on the application's necessity. The proposed circuit consumes low power for RC and buffer chain (34.4, 58.72)mu W respectively.
Randomization,Random bit generator,Variable duty cycle,Machine learning
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