The Optimization of Pin Hole Defect in High Resistance Process
2023 China Semiconductor Technology International Conference (CSTIC)(2023)
摘要
With the continuous shrinkage of the critical dimension and thinning of the film thickness in IC manufacture, the requirements of threshold voltage need advanced performance. However, limited by the structure and material, there is no further improvement of the Gate thickness. Nowadays, the high resistance process (HR) plays the role of separate-voltage which has been widely used to solve this problem. However, the existence of serious pin hole defect issue in traditional HR process leads to the underlying Co missing, which seriously impacts the device performance and limits application of HR process. In this paper, a method was proposed by reducing the SiN etching plasma bombardment capacity and adjusting the etching gas ratio based on dense SiN film, which can solve the issue of pin hole completely and further be applied in IC manufacture.
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关键词
High resistance etch,Pin hole,underlayer damage,defect scan
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