The Research of Special Gate Morphology Adjustment and Its Influence on Electrical Properties

In the key nodes of semiconductor process manufacturing, gate characteristic size, line width uniformity, side wall profile, line width roughness and other characteristics are strictly controlled process parameters. The gate CD of polysilicon directly affects the electrical performance of CMOS devices, and the gate side profile is directly related to the gate performance. In current mainstream Gate processes, Gate profiles are typically “Vertical” side walls. In this paper, the gate side wall profile is successfully change from “Vertical” to “reverse tapered” shape by adjusting the etching process parameters such as ME (Main Etch), SL (Soft Landing), OE (Over Etch), which is greatly beneficial to improve the Dummy-gate removal and subsequent metal filling process window, meanwhile achieves a 2%-3% improvement in the AC Electrical performance of the Device.