Sensitivity Analysis of Memory Bandwidth on Column-superposed Versatile Linear CGRA

The time required for DMA between IMAX's cache memory and ARM's main memory using AXI transactions was a bottleneck for IMAX, a CGRA-type accelerator hosted by an ARM processor and connected via an AXI interface. Therefore, we modified the IMAX accelerator to have eight DMA channels and take full advantage of the AXI interface. Evaluation of a 7200x7200 matrix multiplication without pre-transposition showed that the improved IMAX reduced the time to write input data from ARM main memory to cache memory by about 45% and the overall time by about 20% compared to the conventional IMAX.