Design of DTMOS based third-order G _m -C filter for fast locking PLL

The demand for the high-speed PLL has increased to fulfil the requirement of the present RF communication industry. This paper deals with the designing of a third-order G _m -C loop filter with improved PLL performance. The high gain and low power Operational transconductance amplifier (OTA) is the basic building block of the third order G _m -C filter. The proposed folded cascode (FC) OTA has designed using dynamic threshold MOS (DTMOS) type input differential stage to achieve the dc gain of 77.07 dB, UGB of 25.02 MHz and power consumption of 94.89 μ W. The low power FC OTA design leads to the enhancement in the figure of merits for FOM _S and FOM _L for the small-signal and large-signal operation that is given 4777.07 MHz.pF/mW and 3891.91 V.pF/ μ s.mW, respectively. Further, the third-order reconfigurable G _m -C filter has designed and achieved 25.02 MHz of the cut-off frequency. It consumes power of 283.66 μ W at 1.8 V supply voltage that shows 8.44