Inter-Layer Dielectric Engineering for Monolithic Stacking 4F(2)-2T0C DRAM with Channel-All-Around (CAA) IGZO FET to Achieve Good Reliability (> 10(4)s Bias Stress, > 10(12) Cycles Endurance)

To address the stacking requirement of 4F(2) 2T0C DRAM with vertical channel-all-around (CAA) IGZO FETs, for the first time, the effect of inter-layer dielectric (ILD) on CAA-IGZO FETs has been studied by varying dielectric material and process. By using optimized ILD and IGZO deposition cycle ratio, CAA-IGZO FET with high reliability is obtained. The optimized device exhibits a V-th shift of less than 25 mV after 104s bias stress and no significant degradation after 10(12) cycles endurance. Our results provide an important reference for facilitating the monolithic stacking of multilayer IGZO FETs to realize 3D DRAM.