A Sub-50-fs RMS Jitter, 103.5-GHz Fundamental-Sampling PLL With an Extended Loop Bandwidth

A sub-THz phase-locked loop (PLL) with a power-gating injection-locked frequency multiplier-based phase detector and extended loop bandwidth was designed to achieve ultralow jitter performance and low power consumption. The loop bandwidth of the PLL was extended in two ways to reduce the out-of-band phase noise of a sub-THz voltage-controlled oscillator (VCO) with a low-quality factor. First, the PLL used a separate proportional path to correct the jitter of the VCO directly without passing through the gm-amplifier. Second, a reset switch was used to nullify the effect of the intrinsic infinite-impulse-response (IIR) pole from charge-sharing operation on the loop bandwidth, thus allowing for the further extension of the bandwidth. The proposed sub-THz PLL was fabricated in a 65-nm CMOS process, and it occupied a silicon area of 0.13 mm 2. The proposed sub-THz PLL achieved an RMS jitter of 47 fs using 26.6-mW power, thereby obtaining a jitter FoM of–252 dB at 103.5 GHz.