A 112-Gb/s 58-mW PAM4 Transmitter in 28-nm CMOS Technology.

VLSI Technology and Circuits(2023)

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摘要
A voltage-mode transmitter employs a resistorless output DAC, a 3-tap latchless FFE, a passive output skew compensation network, and a 56-GHz integer-N PLL. The prototype delivers an output swing of $0.8 \mathrm{V}_{{\mathrm {pp,d}}}$ with an rms clock jitter of 160 fs and RLM = 96%.
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关键词
Wireline,PAM4,serializer
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