Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing.

Walid M. Hafez, P. Agnihotri, M. Asoro, M. Aykol, B. Bains, R. Bambery, M. Bapna, A. Barik,A. Chatterjee, P. C. Chiu,T. Chu, C. Firby, K. Fischer, M. Fradkin,Hannes Greve,A. Gupta, E. Haralson,M. Haran, Jeffery Hicks, A. Illa, M. Jang, S. Klopcic, M. Kobrinsky, B. Kuns, H.-h. Lai, G. Lanni,S.-H. Lee, N. Lindert, C.-l. Lo,Y. Luo, G. Malyavanatham, B. Marinkovic, Y. Maymon, M. Nabors, J. Neirynck, P. Packan, A. Paliwal, L. Pantisano, Leif Paulson, Padma Penmatsa,Chetan Prasad, C. Puls, T. Rahman, R. Ramaswamy, S. Samant, B. Sell, K. Sethi, F. Shah, M. Shamanna, K. Shang, Q. Li, M. Sibakoti, J. Stoeger, N. Strutt, R. Thirugnanasambandam, C. Tsai, X. Wang, A. Wang, S.-j. Wu, Q. Xu, X.-h. Zhong, S. Natarajan

VLSI Technology and Circuits（2023）

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摘要

This paper presents a high-yielding backside power delivery (BPD) technology, PowerVia, implemented on Intel 4 finFET process. PowerVia more directly integrates power delivery to the transistor as compared to published buried power rail schemes, enabling additional wiring resources on front side for signal routing. A fabricated E-core with $\gt 90$% cell utilization showed $\gt 30$% platform voltage droop improvement and 6% frequency benefit compared to a similar design without PowerVia. Transistor performance, reliability, and fault isolation capability is detailed.

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