On the Design Challenges of Class-C Oscillators in Ultra-Scaled CMOS Technologies.

A design methodology for class-C oscillators implemented in ultra-scaled technologies is presented. Emphasis is set on the challenge of the minimization of the noise contribution of the bias circuitry, which is particularly relevant due to the increased flicker noise in ultra-scaled technologies. A case study oscillator, in a FinFET 16nm CMOS technology, exhibits a simulated phase noise as low as -116.7 dBc/Hz at 1MHz offset from the 13.2 GHz carrier, while drawing 10.3mA from the 0.95V supply. The simulated tuning range is 44%.