A Novel Parallel Digitizer With a Pulseless Mixing-Filtering-Processing Architecture and Its Implementation in a SiGe HBT Technology at 40GS/s.

Mixing-Filtering-Processing (MFP) digitizers are a class of high-speed digitizers, employing mixers, filters and data converters to obtain high sampling frequencies and large bandwidths. We propose a variant of the Asynchronous Time Interleaving (ATI) architecture which employs synchronous frequencies for the mixers and ADCs, allowing simplified correction of aliasing mismatches via linear filters whose coefficients can be estimated via single-tone tests using well-known linear estimation algorithms. The architecture uses rectangular waves with 50% duty cycle to simplify the hardware implementation and maximize the signal-to-noise ratio of the front-end, thus obtaining a very simple structure requiring few high-frequency analog blocks to implement very fast digitizers: clock dividers, mixers, I/O buffers, and lowpass filters are all that is required to perform MFP digitization, besides the back-end ADCs and the (linear) signal processing for aliasing removal. The proposed architecture is also cascadable and allows the design of multi-channel (4, 8 or more channels) hierarchical MFP digitizers: using the same chip, multiple front-ends can be cascaded to obtain more channels with narrower bandwidth, which can finally be digitized by slower ADCs. The front-end of the two-channel digitizer has been designed in the STMicroelectronics SiGe BiCMOS55 technology, measured, and calibrated. Results prove that aliasing-correction filters can be synthetized and that overall accuracy, after the removal of aliasing terms, is limited by noise and distortions to about 5 equivalent bits from 0 to 20GHz, experimentally validating the calibration technique for mismatch errors.