Systematic Design Methodology for Optimization of Voltage Comparators in CMOS Technology.

The increasing rate of digitalization and the growing use of the Internet-of-Things translate into a rise in demand for sensor-to-digital interface circuits and electronics for processing information. This demand increases the need for a standard workflow, which allows a straightforward comparison between active building-blocks (both amplifiers and comparators) with different architectures. Although comparators are essential building-blocks in many circuit architectures, there is no standard workflow to simulate and compare different circuit topologies. This paper proposes a systematic design workflow to simulate dynamic voltage comparators. The workflow consists of the “testbenches” and a simulation setup for extracting key parameters of comparator performance, such as static-offset, random-offset, worst-case comparison-time for both hard and soft decisions, power dissipation, and input-referred noise. As an example, this paper implements the methodology in Virtuoso environment and presents results for different dynamic comparators in a 28-nm standard bulk-CMOS technology.