Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond

Chih-Hao Chang,V. S. Chang,K. H. Pan, K. T. Lai, J. H. Lu, J. A. Ng,C. Y. Chen,B. F. Wu, C. J. Lin, C. S. Liang,C. P. Tsao, Y. S. Mor, C. T. Li,T. C. Lin,C. H. Hsieh, P. N. Chen, H. H. Hsu,J. H. Chen,H. F. Chen,J. Y. Yeh,M. C. Chiang,C. Y. Lin,J. J. Liaw,C. H. Wang, S. B. Lee,C. C. Chen,H. J. Lin,R. Chen, K. W. Chen,C. O. Chui,Y. C. Yeo,K. B. Huang,T. L. Lee,M. H. Tsai,K. S. Chen,Y. C. Lu,S. M. Jang,S. -Y. Wu

2022 International Electron Devices Meeting (IEDM)（2022）

引用 16|浏览7

关键词

aggressive contacted gate pitch scaling,CMOS technology,contact scheme,critical process features,gate pitch scales,gate stack innovation,improved electrostatics,improved process control,leading-edge CMOS technology,low-k spacer,process robustness,self-aligned contact scheme,size 3.0 nm,size 45.0 nm,size 50.0 nm,storage capacity 256 Mbit,transistor gate count

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