A 13-Level SC DAC Achieving High Linearity With a Simple DEM for Wideband CT DSMs

Wideband continuous-time (CT) Delta-Sigma modulators (DSMs) generally demand multi-level digital-to-analog converters (DACs), which require a linearization technique to overcome the problem of component mismatches. Dynamic element matching (DEM) is a popular DAC linearization approach but can be challenging to implement in a wideband DSM, particularly when there are many DAC elements. In this brief, we introduce a 13-level switched-capacitor (SC) DAC achieving high linearity with a simple DEM that rotates three unit elements only and does not incur excess loop delay. In a traditional CT DSM, a DAC of the SC type increases the amplifier settling requirements and damages the alias rejection. Earlier works have shown that these problems can be solved if the CT DSM adopts a passive RC frontend. A 10-MHz bandwidth CT DSM is designed in the 65-nm CMOS technology to validate the proposed DAC. Simulations show that the DAC enables a spurious-free dynamic range greater than 87.7 dB and a signal-to-noise pulse distortion ratio greater than 80.5 dB under a 1% capacitor mismatch, a 2% reference voltage error, and process variations.