A 12bit 39ps Two-Step Time-to-Digital Converter in 40nm CMOS

Xuxi Liu,Zhao Zhang,Tao Yin,Rui Wu,Peng Feng,Liyuan Liu

2022 IEEE 16th International Conference on Solid-State &amp Integrated Circuit Technology (ICSICT)（2022）

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Key words

0.2-mW power consumption,12-bit dynamic range,39-ps resolution,64-phase multiphase clock generator,clock source,coarse stage,conversion time,dual-edge counter synchronization circuit,fine resolution,fine stage,phase interpolator,phase-locked loop,size 40.0 nm,synchronization error,time 39.0 ps,word length 12.0 bit

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